agileRCOSC
The agileRCOSC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of process variation. This can also be configured as a Free Running Clock (FRC) where a high accuracy clock is not required.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
Start-up time: Typ 10us • Frequency range: 20KHz – 100MHz • Accuracy (Calibrated) Max = ± 5% • Current consumption1: Typ 100uA @ 10MHz • Configurable to your specification • Clean start-up • Trimmable frequency • Low power • Customizable design for simple SoC integration
DFT: Incorporates analog monitor (test) outputs to facilitate ATE test and debug • On chip clock generator
agileRCOSC can be combined with agileCMP, agilePOR and agileBG to create a self-contained, low power, Always On Block (AoB)
Block Diagram | RC Oscillator | agileRCOSC
Take a look at this selection of Agile Analog product and marketing related information. These press releases offer some interesting insights into our industry collaborations and product development work.
