Pioneering platform to create configurable and multi-process analog IP.
Agile Analog is revolutionizing analog IP with our unique platform called Composa™ that automatically generates our customizable and process agnostic analog IP solutions. This novel approach means analog IP can be created to meet your exact requirements, for any foundry and on any process, from legacy nodes right up to the leading edge.
Composa embeds the major foundries’ process development kits (PDKs) and solves the problem of portability of analog IP cores that has traditionally required re-engineering to suit each different silicon process technology. Composa can regenerate the analog IP using a foundry PDK, so it’s simple to make changes, for example, switching to a different foundry or shrinking the chip to suit a smaller node.
Implementing a process-specific re-spin each time you use a different foundry currently takes your valuable engineering effort that could be better focused on value-added differentiating design work. Using our analog IP cores in your designs removes the hassle associated with standard analog IP. We can automatically generate new versions of our IP using the PDK for a different foundry, so you can change foundries and take advantage of available capacity.
Access to any process technology also helps if you are planning to move to a next generation smaller process node. The majority of enhancements usually occur in the digital implementation, whereas the analog IP which provides analog functionality, such as data conversion and power management, typically remains constant. Having this IP regenerated by Agile Analog for a smaller process node means you don’t have to process port all analog circuits.
Composa production flow diagram
To produce our analog IP we use tried and tested analog IP circuits that are in our Composa library. Effectively, the design-once-and-re-use-many-times model of digital IP now applies to analog IP for the first time. The analog IP circuits in our Composa library have been extensively tested and used in previous designs, and are fully validated. This gives a similar level of reassurance and risk mitigation to the digital IP world’s ‘silicon-proven’.
Our Composa platform is qualified by the world’s major foundries. As our IP is generated automatically and fully tested, it’s defect-free. The IP is also backed by the industry’s most comprehensive support and rigorous set of IP Deliverables - test specifications, documentation, simulation outputs and verification models. So, when you tape out your chip, one thing that you don’t need to worry about is the Agile Analog IP inside.
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