agileREF
The agileREF consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of output bias currents can be specified up to a maximum of 16 configurable outputs. There is an integrated test bus.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Input voltage range: PDK VddIO • Programmable output voltage range • Untrimmed accuracy: 5% • Trimmed accuracy (single point trim): 0.5% • Bias current output: 1uA to 100uA • Quiescent current (Iq): 50uA typical • Customizable design for simple SoC integration • Silicon area – Please contact Agile Analog
Low Iq: Low current consumption for power sensitive applications • Multiple outputs: Low current consumption for power sensitive applications
The bandgap is an essential analog IP for all system designs
Block Diagram | General Purpose BandGap Reference | agileREF
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