agilePMU
The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs. Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Assertion time: 5us (typ) • Configurable trigger thresholds • Programmable delay • Current consumption: 1.5uA (typ)
Output voltage: Programmable • Load current: User defined • Active current: 1uA (typ) • Power down current: 10nA (typ) • PSRR: 40dB (@DC)
Start-up time: Typ 20us • Industry standard digital interface • Configurable logic to control sequencing and monitoring • Fully integrated macro •Standard AMBA APB interface
Block Diagram | Power Management Subsystem | agilePMU
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