Documents

Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature.

This provides more detailed guidance on the integration process.

Outlining key parameters to check pre-tapeout.

This is a pin-exact Verilog A model, intended to be used for analog system validation in the case that the component is used as part of an analog pipeline.

This is a pin-exact Verilog file, intended for floorplanning and high level digital integration. This is a black-box only, and has no internal functionality.

This is a pin-exact Verilog file, intended for simulation and verification of the integration process.

This is a pin-exact LEF model, intended for floorplanning purposes. This provides an estimate of the area of the design, and can be used for top level floorplanning of the design. We aim for this to be a realistic estimate and we will always strive to deliver a final layout that fits within the LEF file boundary.

These files provide a complete timing model for the design. These are provided per-corner, and should be loaded combined with the Verilog stub for the design when read into the place and route tool. Depending on the block, these are either generated through Innovus as black-box timing models, or generated using Liberate. These files are expected to change between IDP and FDP as the design is finalized.

This file includes the complete transistor-level netlist for the IP, uniquified such that any standard-cells or other common blocks will not clash names at the SoC level. This file should be used to confirm LVS results at block level, and to perform LVS at SoC level.

This file includes the complete layout for the IP. The layer-map should be verified on import, to ensure that all layers present are imported into the SoC database. The GDS has been uniquified, such that any standard-cells or other common blocks will not clash names at the SoC level. This file should be used to confirm LVS and DRC results at block level.

This directory includes the DRC, LVS, ERC checks performed by Agile Analog on the final CDL and GDS prior to release. Any waivers will refer to these reports, and the customer should be able to recreate these reports. Any differences should immediately be flagged.

Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature.

Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature.